/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_MAMPUWP_H_
#define CSLR_MAMPUWP_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 DBG_HWWP_CAP;
    volatile Uint32 TRIG_CTRL;
    volatile Uint32 DBG_HWWP0_LW_ADDR0;
    volatile Uint32 DBG_HWWP0_HG_ADDR0;
    volatile Uint32 DBG_HWWP0_MAIN_CNTL;
    volatile Uint32 DBG_HWWP0_AUX_CNTL;
    volatile Uint32 DBG_HWWP0_MEM_CNTL;
    volatile Uint32 DBG_HWWP0_CHAIN_CNTL;
    volatile Uint32 DBG_HWWP0_LW_ADDR0_LOG;
    volatile Uint32 DBG_HWWP0_HG_ADDR0_LOG;
    volatile Uint32 DBG_HWWP0_DATA0_LOG;
    volatile Uint32 DBG_HWWP0_DATA1_LOG;
    volatile Uint32 DBG_HWWP0_DATA2_LOG;
    volatile Uint32 DBG_HWWP0_DATA3_LOG;
    volatile Uint32 DBG_HWWP0_TRANS_ATTR0_LOG;
    volatile Uint32 DBG_HWWP0_TRANS_ATTR1_LOG;
    volatile Uint32 DBG_HWWP0_DATA_TRANS_ATTR0_LOG;
} CSL_MampuWpRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* Debug Watchpoint Capabilities Register */
#define CSL_MAMPUWP_DBG_HWWP_CAP                                (0x0U)

/* Trigger control 1: External trigger (TRIGOUT) will fire 0: External trigger
 * (TRIGOUT) will not fire */
#define CSL_MAMPUWP_TRIG_CTRL                                   (0x4U)

/* Debug WatchPoint Addr0 for low order bits */
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0                          (0x8U)

/* Debug WatchPoint Addr0 for high order bits */
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0                          (0xCU)

/* Debug WatchPoint Main Control Register */
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL                         (0x10U)

/* Debug WatchPoint Auxilliary Control Register */
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL                          (0x14U)

/* Debug WatchPoint Memory Barrier Control */
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL                          (0x18U)

/* Debug WatchPoint Data/Memory Barrier Chain Control Register */
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL                        (0x1CU)

/* Debug WatchPoint Addr0 for low order bits log register. THIS REGISTER IS
 * RESET UPON 0->1 TRANSITION OF WP_EN. */
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG                      (0x20U)

/* Debug WatchPoint Addr0 for high order bits log register. THIS REGISTER IS
 * RESET UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG                      (0x24U)

/* Debug WatchPoint Data Log register (bits 31:0). THIS REGISTER IS RESET UPON
 * 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG                         (0x28U)

/* Debug WatchPoint Data Log register (bits 63:32). THIS REGISTER IS RESET
 * UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG                         (0x2CU)

/* Debug WatchPoint Data Log register (bits 95:64). THIS REGISTER IS RESET
 * UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG                         (0x30U)

/* Debug WatchPoint Data Log register (bits 125:96). THIS REGISTER IS RESET
 * UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG                         (0x34U)

/* Debug WatchPoint Transaction Attributes 0 Log Register. THIS REGISTER IS
 * RESET UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG                   (0x38U)

/* Debug WatchPoint Transaction Attributes 1 Log Register. THIS REGISTER IS
 * RESET UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG                   (0x3CU)

/* Debug WatchPoint Data Transaction Attributes 0 Log Register. THIS REGISTER
 * IS RESET UPON 0->1 TRANSITION OF WP_EN */
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG              (0x40U)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* DBG_HWWP_CAP */

#define CSL_MAMPUWP_DBG_HWWP_CAP_RES_MASK                       (0xFFFF0000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES_SHIFT                      (16U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES_RESETVAL                   (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES_MAX                        (0x0000ffffU)

#define CSL_MAMPUWP_DBG_HWWP_CAP_NUM_WP_MASK                    (0x0000000FU)
#define CSL_MAMPUWP_DBG_HWWP_CAP_NUM_WP_SHIFT                   (0U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_NUM_WP_RESETVAL                (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_NUM_WP_MAX                     (0x0000000fU)

#define CSL_MAMPUWP_DBG_HWWP_CAP_ADDR_WIDTH_MASK                (0x00000070U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_ADDR_WIDTH_SHIFT               (4U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_ADDR_WIDTH_RESETVAL            (0x00000005U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_ADDR_WIDTH_MAX                 (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_RES1_MASK                      (0x00000080U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES1_SHIFT                     (7U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES1_RESETVAL                  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES1_MAX                       (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_DATA_WIDTH_MASK                (0x00000700U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_DATA_WIDTH_SHIFT               (8U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_DATA_WIDTH_RESETVAL            (0x00000004U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_DATA_WIDTH_MAX                 (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_RES2_MASK                      (0x00000800U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES2_SHIFT                     (11U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES2_RESETVAL                  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_RES2_MAX                       (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_AUX_CNTL_REG_PRESENT_MASK  (0x00001000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_AUX_CNTL_REG_PRESENT_SHIFT  (12U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_AUX_CNTL_REG_PRESENT_RESETVAL  (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_AUX_CNTL_REG_PRESENT_MAX  (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR0_REG_PRESENT_MASK  (0x00002000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR0_REG_PRESENT_SHIFT  (13U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR0_REG_PRESENT_RESETVAL  (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR0_REG_PRESENT_MAX  (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR1_REG_PRESENT_MASK  (0x00004000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR1_REG_PRESENT_SHIFT  (14U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR1_REG_PRESENT_RESETVAL  (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_TRANS_ATTR1_REG_PRESENT_MAX  (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_MEM_CHAIN_REG_PRESENT_MASK  (0x00008000U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_MEM_CHAIN_REG_PRESENT_SHIFT  (15U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_MEM_CHAIN_REG_PRESENT_RESETVAL  (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP_CAP_HWWP_MEM_CHAIN_REG_PRESENT_MAX  (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP_CAP_RESETVAL                       (0x0000f451U)

/* TRIG_CTRL */

#define CSL_MAMPUWP_TRIG_CTRL_RES_MASK                          (0xFFFFFFFEU)
#define CSL_MAMPUWP_TRIG_CTRL_RES_SHIFT                         (1U)
#define CSL_MAMPUWP_TRIG_CTRL_RES_RESETVAL                      (0x00000000U)
#define CSL_MAMPUWP_TRIG_CTRL_RES_MAX                           (0x7fffffffU)

#define CSL_MAMPUWP_TRIG_CTRL_TRIG_EN_MASK                      (0x00000001U)
#define CSL_MAMPUWP_TRIG_CTRL_TRIG_EN_SHIFT                     (0U)
#define CSL_MAMPUWP_TRIG_CTRL_TRIG_EN_RESETVAL                  (0x00000000U)
#define CSL_MAMPUWP_TRIG_CTRL_TRIG_EN_MAX                       (0x00000001U)

#define CSL_MAMPUWP_TRIG_CTRL_RESETVAL                          (0x00000000U)

/* DBG_HWWP0_LW_ADDR0 */

#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOWER_ORDER_WP_ADDR_MASK  (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOWER_ORDER_WP_ADDR_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOWER_ORDER_WP_ADDR_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOWER_ORDER_WP_ADDR_MAX  (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_RESETVAL                 (0x00000000U)

/* DBG_HWWP0_HG_ADDR0 */

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_HIGHER_ORDER_WP_ADDR_MASK  (0x000000FFU)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_HIGHER_ORDER_WP_ADDR_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_HIGHER_ORDER_WP_ADDR_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_HIGHER_ORDER_WP_ADDR_MAX  (0x000000ffU)

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_RES_MASK                 (0xFFFFFF00U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_RES_SHIFT                (8U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_RES_RESETVAL             (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_RES_MAX                  (0x00ffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_RESETVAL                 (0x00000000U)

/* DBG_HWWP0_MAIN_CNTL */

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_TRIG_MASK               (0x80000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_TRIG_SHIFT              (31U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_TRIG_RESETVAL           (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_TRIG_MAX                (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES_MASK                (0x7F000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES_SHIFT               (24U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES_RESETVAL            (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES_MAX                 (0x0000007fU)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_BEAT_SEL_MASK           (0x00F00000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_BEAT_SEL_SHIFT          (20U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_BEAT_SEL_RESETVAL       (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_BEAT_SEL_MAX            (0x0000000fU)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES1_MASK               (0x000E0000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES1_SHIFT              (17U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES1_RESETVAL           (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES1_MAX                (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES3_MASK               (0x00010000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES3_SHIFT              (16U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES3_RESETVAL           (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES3_MAX                (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SUPERVISOR_USER_ACCESS_MASK  (0x0000C000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SUPERVISOR_USER_ACCESS_SHIFT  (14U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SUPERVISOR_USER_ACCESS_RESETVAL  (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SUPERVISOR_USER_ACCESS_MAX  (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SECURE_ACCESS_MASK      (0x00003000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SECURE_ACCESS_SHIFT     (12U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SECURE_ACCESS_RESETVAL  (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_SECURE_ACCESS_MAX       (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES2_MASK               (0x00000800U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES2_SHIFT              (11U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES2_RESETVAL           (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RES2_MAX                (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_ADDR_MASK_MASK       (0x000007E0U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_ADDR_MASK_SHIFT      (5U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_ADDR_MASK_RESETVAL   (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_ADDR_MASK_MAX        (0x0000003fU)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_MATCH_CRITERIA_MASK  (0x00000010U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_MATCH_CRITERIA_SHIFT  (4U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_MATCH_CRITERIA_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_MATCH_CRITERIA_MAX   (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_LS_ACCESS_MASK       (0x0000000EU)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_LS_ACCESS_SHIFT      (1U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_LS_ACCESS_RESETVAL   (0x00000007U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_LS_ACCESS_MAX        (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_EN_MASK              (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_EN_SHIFT             (0U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_EN_RESETVAL          (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_WP_EN_MAX               (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MAIN_CNTL_RESETVAL                (0x0000f00eU)

/* DBG_HWWP0_AUX_CNTL */

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES_MASK                 (0xFFFF0000U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES_SHIFT                (16U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES_RESETVAL             (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES_MAX                  (0x0000ffffU)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_MA_SPLIT_TARG_MASK       (0x0000C000U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_MA_SPLIT_TARG_SHIFT      (14U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_MA_SPLIT_TARG_RESETVAL   (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_MA_SPLIT_TARG_MAX        (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES1_MASK                (0x00003F80U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES1_SHIFT               (7U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES1_RESETVAL            (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES1_MAX                 (0x0000007fU)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_INITIATOR_ID_MASK        (0x00000070U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_INITIATOR_ID_SHIFT       (4U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_INITIATOR_ID_RESETVAL    (0x00000007U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_INITIATOR_ID_MAX         (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES2_MASK                (0x0000000CU)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES2_SHIFT               (2U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES2_RESETVAL            (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RES2_MAX                 (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_ACCESS_TYPE_MASK         (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_ACCESS_TYPE_SHIFT        (0U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_ACCESS_TYPE_RESETVAL     (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_ACCESS_TYPE_MAX          (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_AUX_CNTL_RESETVAL                 (0x0000c073U)

/* DBG_HWWP0_MEM_CNTL */

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TRIG_MASK        (0x80000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TRIG_SHIFT       (31U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TRIG_RESETVAL    (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TRIG_MAX         (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_RES1_MASK                (0x7FFFFFE0U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_RES1_SHIFT               (5U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_RES1_RESETVAL            (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_RES1_MAX                 (0x03ffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TYPE_MASK        (0x00000006U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TYPE_SHIFT       (1U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TYPE_RESETVAL    (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_TYPE_MAX         (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_WP_EN_MASK       (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_WP_EN_SHIFT      (0U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_WP_EN_RESETVAL   (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_WP_EN_MAX        (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_ACCESS_TYPE_MASK  (0x00000018U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_ACCESS_TYPE_SHIFT  (3U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_ACCESS_TYPE_RESETVAL  (0x00000003U)
#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_MEM_BAR_ACCESS_TYPE_MAX  (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_MEM_CNTL_RESETVAL                 (0x0000001eU)

/* DBG_HWWP0_CHAIN_CNTL */

#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_TRIG_MASK     (0x80000000U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_TRIG_SHIFT    (31U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_TRIG_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_TRIG_MAX      (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_RES1_MASK              (0x7FFFFFFCU)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_RES1_SHIFT             (2U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_RES1_RESETVAL          (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_RES1_MAX               (0x1fffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_TYPE_MASK        (0x00000002U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_TYPE_SHIFT       (1U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_TYPE_RESETVAL    (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_TYPE_MAX         (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_EN_MASK       (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_EN_SHIFT      (0U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_EN_RESETVAL   (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_CHAIN_WP_EN_MAX        (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_CHAIN_CNTL_RESETVAL               (0x00000000U)

/* DBG_HWWP0_LW_ADDR0_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG_WP_ADDR_LOWER_ORDER_BITS_MASK  (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG_WP_ADDR_LOWER_ORDER_BITS_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG_WP_ADDR_LOWER_ORDER_BITS_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG_WP_ADDR_LOWER_ORDER_BITS_MAX  (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_LW_ADDR0_LOG_RESETVAL             (0x00000000U)

/* DBG_HWWP0_HG_ADDR0_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_RES_MASK             (0xFFFFFF00U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_RES_SHIFT            (8U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_RES_RESETVAL         (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_RES_MAX              (0x00ffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_WP_ADDR_HIGHER_ORDER_BITS_MASK  (0x000000FFU)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_WP_ADDR_HIGHER_ORDER_BITS_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_WP_ADDR_HIGHER_ORDER_BITS_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_WP_ADDR_HIGHER_ORDER_BITS_MAX  (0x000000ffU)

#define CSL_MAMPUWP_DBG_HWWP0_HG_ADDR0_LOG_RESETVAL             (0x00000000U)

/* DBG_HWWP0_DATA0_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG_DATA0_CAPTURE_MASK      (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG_DATA0_CAPTURE_SHIFT     (0U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG_DATA0_CAPTURE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG_DATA0_CAPTURE_MAX       (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA0_LOG_RESETVAL                (0x00000000U)

/* DBG_HWWP0_DATA1_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG_DATA1_CAPTURE_MASK      (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG_DATA1_CAPTURE_SHIFT     (0U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG_DATA1_CAPTURE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG_DATA1_CAPTURE_MAX       (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA1_LOG_RESETVAL                (0x00000000U)

/* DBG_HWWP0_DATA2_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG_DATA2_CAPTURE_MASK      (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG_DATA2_CAPTURE_SHIFT     (0U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG_DATA2_CAPTURE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG_DATA2_CAPTURE_MAX       (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA2_LOG_RESETVAL                (0x00000000U)

/* DBG_HWWP0_DATA3_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG_DATA3_CAPTURE_MASK      (0xFFFFFFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG_DATA3_CAPTURE_SHIFT     (0U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG_DATA3_CAPTURE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG_DATA3_CAPTURE_MAX       (0xffffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA3_LOG_RESETVAL                (0x00000000U)

/* DBG_HWWP0_TRANS_ATTR0_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_TYPE_MASK   (0x00000007U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_TYPE_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_TYPE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_TYPE_MAX    (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_LENGTH_MASK  (0x000003F0U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_LENGTH_SHIFT  (4U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_LENGTH_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_BURST_LENGTH_MAX  (0x0000003fU)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TRANS_TYPE_MASK   (0x00001C00U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TRANS_TYPE_SHIFT  (10U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TRANS_TYPE_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TRANS_TYPE_MAX    (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES1_MASK         (0x0000E000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES1_SHIFT        (13U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES1_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES1_MAX          (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TARGET_INFO_MASK  (0x00070000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TARGET_INFO_SHIFT  (16U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TARGET_INFO_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_TARGET_INFO_MAX   (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES2_MASK         (0x00080000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES2_SHIFT        (19U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES2_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES2_MAX          (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_INIT_INFO_MASK    (0x00700000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_INIT_INFO_SHIFT   (20U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_INIT_INFO_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_INIT_INFO_MAX     (0x00000007U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES3_MASK         (0x00800000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES3_SHIFT        (23U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES3_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES3_MAX          (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RESP_INFO_MASK    (0x03000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RESP_INFO_SHIFT   (24U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RESP_INFO_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RESP_INFO_MAX     (0x00000003U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES4_MASK         (0xFC000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES4_SHIFT        (26U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES4_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES4_MAX          (0x0000003fU)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES_MASK          (0x00000008U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES_SHIFT         (3U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES_RESETVAL      (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RES_MAX           (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR0_LOG_RESETVAL          (0x00000000U)

/* DBG_HWWP0_TRANS_ATTR1_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SECURE_MASK       (0x00000001U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SECURE_SHIFT      (0U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SECURE_RESETVAL   (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SECURE_MAX        (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SUPERVISOR_MASK   (0x00000002U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SUPERVISOR_SHIFT  (1U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SUPERVISOR_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_SUPERVISOR_MAX    (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_DATA_MASK         (0x00000004U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_DATA_SHIFT        (2U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_DATA_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_DATA_MAX          (0x00000001U)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_RES1_MASK         (0xFFFFFFF8U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_RES1_SHIFT        (3U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_RES1_RESETVAL     (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_RES1_MAX          (0x1fffffffU)

#define CSL_MAMPUWP_DBG_HWWP0_TRANS_ATTR1_LOG_RESETVAL          (0x00000000U)

/* DBG_HWWP0_DATA_TRANS_ATTR0_LOG */

#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_RES_MASK     (0xFFFF0000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_RES_SHIFT    (16U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_RES_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_RES_MAX      (0x0000ffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_BYTE_EN_MASK  (0x0000FFFFU)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_BYTE_EN_SHIFT  (0U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_BYTE_EN_RESETVAL  (0x00000000U)
#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_BYTE_EN_MAX  (0x0000ffffU)

#define CSL_MAMPUWP_DBG_HWWP0_DATA_TRANS_ATTR0_LOG_RESETVAL     (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
